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.Thegoal is to create faster code which minimises the processor load.Chapter ObjectivesAfter completing this chapter, you are able to:" Describe methods of improving the CP capacity" Declare data in a memory-efficient wayFigure 12.1Chapter ObjectivesConceptsAXE exchanges become more and more powerful, offer new services andinclude new functions.The consequence is that the number of blocks, jobs,signals and variables increases constantly.In spite of ever bigger and fasterprocessor hardware, the explosion in software prevents contemporaryexchanges from processing traffic faster than ten years ago.Therefore, every designer should strive to keep the processor load as lowas possible.For more information see chapters Real Time in reference [3]and Designing Capacity-Efficient Software in reference [1].DefinitionsProcessor Load.The part of time the processor executes work on bufferlevel C and higher.Thus, D-level jobs do not contribute to the processorload.Unit: percent.Processor load consists of idle load, traffic load and usage load.Idle Load.Processor work which does not depend on traffic or externalactivities.Example: job table scanning.Traffic Load.Processor work which results from traffic handling, namelycalls, messages or handovers.Usage Load.Processor work which results from operation and mainte-nance activities during busy hours, namely command execution, datadumps and traffic measurement printouts.217 Plex-C 2Processor Capacity.The number of tasks the processor executes per sec-ond.Unit: number of instructions per second, or millions of instructionsper second (MIPS).Efficient Data DesignTable 12.1 compares the access times for different types of variables, seealso reference [1].Always give preference to temporary variables if theprogram is time-critical.APZ 211 11 APZ 212 11one ten one tenVariable typeaccess accesses access accessesTemporary 0.16 0.2Common DS 0.81 0.4Structured 0.98 0.5Record 0.98 0.6Indexed 0.98 9.8/7.1a 0.6 6.0/3.6bIndexed 2-dimensional 1.14 1.1Dynamic buffer 6.75 66.0/15.5c 2.3 23.0/5.3da.Read from Store Indexed (RSI)b.Read from Store Indexed (RSI)c.Read Dynamic Buffer Indexed (RDBI)d.Read Dynamic Buffer Indexed (RDBI)Table 12.1Typical access times per variable typeThe table shows clearly which variables ensure fast access.Always usetemporary variables if the program permits.ARRAYS.Indexed variables are effective when the program needs toread or write a lot of data.Since the data is stored consecutively in thememory, the ASA program can use fast instructions to read from and writeinto the memory.Example: reading ten consecutive array elements takes7.1 µ s instead of 9.8 µ s when using ASA read statement RSI instead ofRS.BUFFER.BUFFER variables take the most CP time by far.AvoidBUFFER variables as much as possible, except in file-oriented input/out-put tasks and when sharing large quantities of data between different CPSW units.See reference [1], section Dynamic Buffers, for more details.218 Efficient DesignImproved Use of MemoryThe contents of program store and data store grow rapidly.Even if mem-ory is rather inexpensive, do not waste memory either.An ever-growingdata store can also take CP capacity to administer the memory.Useful Hints" Record variables are most critical, since they take space in hundreds orthousands of records.So, verify that all record variables are really nec-essary." Investigate if it is possible to transfer some record variables into com-mon stored or temporary variables." Avoid symbol variables in records.Investigate if it is possible toreplace a symbol variable with a field variable which may be smaller,or merge several symbol variables into one." Validate all RELOAD variables.Make sure they are not set in therestart subprogram, otherwise there is no need to declare them asRELOAD." With linked lists, investigate if the program really needs a double-linked list or if a single-linked list can do the job too.Efficient Program DesignSignals" Avoid data value + in signal sending statements.The receiving SWunit should decide whether or not all the signal data are relevant." Try to keep the signal data words in the same CP registers by keepingthe place and order of the signal data in signal reception and signalsending statements.Add new signal data at the end of the signal datawords.This strategy saves a few MFR (Move From Register) state-ments." Reduce the number of IFs, tests and cases after receiving a signal.Limit the number of various conditions and situations, and combinethem into certain states.Consider the example in Figure 12.2.219 Plex-C 2ENTER SIGNAL WITH D1, D2, D3;IF D1 = A THENIF D2 = B THENCASE D3 ISBADWHEN 1 DO.WHEN 2 DO.CODEOTHERWISE DO
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